Engineering Station allows designers and test engineers to verify and to debug boards and systems using the full potential of the benefits brought by Boundary-scan and the JTAG (IEEE 1149.1) standard.

It includes all the functionality you need to : define Unit Under Test (UUT), check BSDL, verify scan chain integrity (infrastructure tests), perform interconnect tests, create complex functional tests using TCL language and to execute diagnostics on nets and signals. This station allows you to declare your board and build a debugging project in a few hours, which leaves you more time for your debugging !

One of the key advantages of DiaTem Studio is the providing of a static analysis of test coverage and the ability to check testability during the design process.

This analysis is linked to a Net Navigator that quickly leverages your understanding of what can be improved in the JTAG testability. The benefit is that you can be sure that your DfT is optimized before manufacturing the boards.

A new version of the Board Manager adds more flexibility, control and enhanced performance. It introduces Virtual Board and Virtual Component entities into the hierarchy of a project. You can thus choose to mount a virtual component available in your hierarchy to simply implement this one into your physical JTAG chain.