Designed to be independent from any FPGA or PLD target, DiaLite tool fits easily with any standard design flow that uses a HDL synthesis tool.
During the Design Level of your hardware, the DiaLite Core library allows you to choose and insert the IP instruments you need to perform your debug process.
At this Debug Level, you are now ready for the "Chip Debugging" step of the process. Your design runs jointly with your embedded instrumentation while DiaLite provides you with all the tools to Control and Display your IP cores.
You can now easily debug your design at speed, analyze logic signal levels and transactions, monitor busses and record logic events.
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Debug cores are then automatically generated with the provided parameters and connected to the internal signals and busses.
These cores are inserted into Verilog or VHDL code. The design is then synthesized, placed and routed using the most current synthesis tools available on the market. The bitstreams are finally downloaded into the FPGA with a JTAG controller device.
On-Chip Instrumentation & Debug without any constraint